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Preliminary Technical Data
FEATURES
Dual Independent Digitally Controlled VGAs -4 to 20dB Gain Range 1 dB Step Size 0.2 dB Differential input and output 150 Differential Input Open Collector Differential Output 8.7 dB noise figure @ maximum gain OIP3 of ~50dBm at 140MHz -3 dB bandwidth of 700 MHz Excellent Channel to Channel Isolation Two Parallel 5-bit Control Interfaces Wide input dynamic range Power-down Control Single 5V Supply Operation 32 Lead LFCSP 5 x 5 mm Package
Ultra Low Distortion IF Dual VGA AD8376
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Differential ADC drivers Main and Diverstiy IF Sampling Receivers High Output Power IF Amplification Multi-channel Receivers Instrumentation
Figure 1.
GENERAL DESCRIPTION
The AD8376 is a dual channel digitally controlled, variable gain wide bandwidth amplifier that provides precise gain control, high IP3 and low noise figure. The excellent distortion performance and high signal bandwidth makes the AD8376 an excellent gain control device for a variety of receiver applications. For wide input dynamic range applications, the AD8376 provides a broad 24 dB gain range with 1 dB resolution. The gain of each channel is adjusted through dedicated 5-pin control interfaces and can be driven using standard TTL levels. The open-collector outputs provide a flexible interface, allowing the overall signal gain to be set by the loading resistance. The AD8376 offers a maximum trans-conductance gain of 67 m-1's. This results in a signal voltage gain proportional to the load resistance. When driving a 150 differential load, the maximum signal gain will be 20 dB. Using a high speed SiGe process and incorporating proprietary distortion cancellation techniques, the AD8376 achieves 50 dBm output IP3 at 140 MHz. Each channel of the AD8376 can be individually powered on by applying the appropriate logic level to the ENBA and ENBB power enable pins. The quiescent current of the AD8376 is typically 130 mA per channel. When powered down, the AD8376 consumes less than 5mA and offers excellent input to output isolation, lower than -50 dB at 200 MHz. Fabricated on an ADI's high speed SiGe process, the AD8376 provides precise gain adjustment capabilities with good distortion performance. The AD8376 amplifier comes in a compact, thermally enhanced 5 x 5mm 32-lead LFCSP package and operates over the temperature range of -40C to +85C.
Rev. PrD
March 13, 2007
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2007 Analog Devices, Inc. All rights reserved.
AD8376 SPECIFICATIONS
Preliminary Technical Data
VS = 5 V, T = 25C, RS = RL = 150 at 100MHz, 2 V p-p differential output, both channels enabled, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate INPUT STAGE Maximum Input Swing Differential Input Resistance Common-Mode Input Voltage CMRR GAIN Amplifier Transconductance Maximum Voltage Gain Minimum Voltage Gain Gain Step Size Gain Flatness Gain Temperature Sensitivity Gain Step Response OUTPUT STAGE Output Voltage Swing Output impedance Channel Isolation (Worst Case) NOISE/HARMONIC PERFORMANCE 46 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 70 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 140 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point Conditions VOUT < 2 V p-p (5.2dBm) Min Typ 700 TBD TBD 150 1.9 TBD 0.058 0.067 20 -4 0.8 1.0 TBD TBD TBD 10 5k/1 -53 1.2 Max Unit MHz V/nsec
Pins IPA+ and IPA-, IPB+ and IPBFor linear operation (AV = -4 dB) Differential Gain Code = 00000 Gain Code = 00000 Gain Code = 00000 Gain Code 11000 From Gain Code 00000 to 11000 Gain Code = 00000 over 20% fractional bandwidth for fC < 200MHz Gain Code = 00000 For VIN = 100mVp-p, Gain Code 10100 to 00000 Pins OPA+ and OPA-, OPB+ and OPBAt P1dB, Gain Code = 00000 Differential Measured at differential output for differential input applied to alternate channel Gain Code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, +3 dBm per tone Gain Code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, +3 dBm per tone Gain Code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, +3 dBm per tone 8.7 -86 -91 50 19 dB dBc dBc dBm dBm 8.7 -94 -92 50 19 dB dBc dBc dBm dBm 8.7 -94 -92 50 19 dB dBc dBc dBm dBm
TBD
V p-p V dB -1 dB dB dB dB mdB/C ns V p-p /pF dB
0.076
Rev PrD | Page 2 of 12
Preliminary Technical Data
Parameter 200 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point POWER-INTERFACE Supply Voltage Quiescent Current Per Channel vs. Temperature Power Down Current Per Channel vs. Temperature POWER-UP/GAIN CONTROL VIH VIL Logic Input Bias Current Conditions Gain Code = 00000 VOUT = 2 V p-p VOUT = 2 V p-p 2 MHz spacing, +3 dBm per tone Min Typ 8.7 -85 -87 50 18 4.5 Thermal connection made to exposed paddle under device, both channels enabled -40C TA +85C PWUP Low -40C TA +85C Pins A0 - A4, B0 - B4, PUPA, and PUPB 5.0 130 5.5 140 155 3 TBD Max Unit dB dBc dBc dBm dBm V mA mA mA mA V 0.8 900 nA
AD8376
TBD
Minimum voltage for a logic high Maximum voltage for a logic low
1.6
Table 2. Gain-Code versus Voltage Gain Look-Up Table
5-Bit Binary Gain Code 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 Voltage Gain (dB) 20 19 18 17 16 15 14 13 12 11 10 9 8 5-Bit Binary Gain Code 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 >11000 Voltage Gain (dB) 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -4
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AD8376 ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage, VPOS ENBA, ENBB, A0-A4, B0-B4 Input Voltage, VIN+ ,VINInternal Power Dissipation JA (Exposed paddle soldered down) JA (Exposed paddle not soldered down) JC (At exposed paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 5.5 V -0.6 to (VPOS + 0.6V) -0.6 to +3.1V TBD mW TBDC/W TBDC/W TBDC/W TBDC -40C to +85C -65C to +150C TBDC
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev PrD | Page 4 of 12
Preliminary Technical Data PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
AD8376
Figure 2. 32 Lead LFCSP
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13, 20 14 15, 17 16, 18 19 21, 28 22 23, 25 24. 26 27 29 30 31 32 Mnemonic A2 A3 A4 VCMA VCMB B4 B3 B2 B1 B0 IPB+ IPBGNDB VCCB OPB+ OPBENBB GNDA ENBA OPAOPA+ VCCA IPAIPA+ A0 A1 Description MSB-2 for the Gain Control Interface for Channel A. MSB-1 for the Gain Control Interface for Channel A. The MSB for the 5-bit Gain Control Interface for Channel A. Channel A Input Common Mode Voltage. Typically bypassed to ground through capacitor Channel B Input Common Mode Voltage. Typically bypassed to ground through capacitor The MSB for the 5-bit Gain Control Interface for Channel B. MSB-1 for the Gain Control Interface for Channel B. MSB-2 for the Gain Control Interface for Channel B. LSB+1 for the Gain Control Interface for Channel B. LSB for the Gain Control Interface for Channel B. Channel B Positive Input. Channel B Negative Input. Device Common (DC Ground) for Channel B. Positive Supply Pin for Channel B. Should be bypassed to Ground using suitable bypass capacitor. Positive Ouptut Pins (Open Collector) for Channel B. Require DC bias of +5V nominal. Negative Ouptut Pins (Open Collector) for Channel B. Require DC bias of +5V nominal. Power Enable Pin for Channel B. Device Common (DC Ground) for Channel A. Power Enable Pin for Channel A. Negative Ouptut Pins (Open Collector) for Channel A. Require DC bias of +5V nominal. Positive Ouptut Pins (Open Collector) for Channel A. Require DC bias of +5V nominal. Positive Supply Pins for Channel A. Should be bypassed to Ground using suitable bypass capacitor. Channel A Negative Input. Channel A Positive Input. LSB for the Gain Control Interface for Channel A. LSB+1 for the Gain Control Interface for Channel A.
Rev PrD | Page 5 of 12
AD8376 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25C, RSource = RLoad = 150 , both channels enabled, unless otherwise noted.
25 20 15 POWER GAIN (dB) 10
IP3 (dBm) 50 55
Preliminary Technical Data
Av = 20 dB Av = 20 dB Av = 10 dB
5 0 -5 -10 -15 -20 -25 -30 10E+06 Av = -4 dB
Av = 0 dB
45
Av = -4 dB
40
100E+06
1E+09
10E+09
40
90
FREQUENCY (Hz)
140 FREQUENCY (MHz)
190
240
Figure 2. Gain vs. Frequency by Gain Code, (all codes), Differential-in, Differential-out
22 HARMONIC DISTORTION (dBc) . 21.5 21 OP1dB (dBm) 20.5 20 19.5 19 18.5 18 -5 0 5 GAIN (dB) 10 15 20
Figure 5. Output IP3 vs. Frequency (20, 10, 0, -4 dB gain codes), 3 dBm tones with 2 MHz spacing
-70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -5 -4 -3 -2 -1 0 1 2 3 4 5 OUTPUT POWER (dBm) Av = 20 dB HD3 Av = 10 Av = 0 dB Av = 10 dB Av = -4 dB Av = 20 dB Av = -4 dB Av = 0 dB HD2
100 MHz 150 MHz 200 MHz 250 MHz
Figure 3. P1dB vs. Gain at Various Frequencies
Figure 6. HD2 and HD3 vs. Power Out (20, 10, 0, -4 dB gain codes) at 140 MHz
45
55 Av = 20 dB Av = 10 dB NOISE FIGURE (dB) . 50 IP3 (dBm)
40 35 30 25 20 15 10 5 Av = 20 dB Av = 10 dB Av = 0 dB Av = -4 dB
45
Av = -4 dB 40
Av = 0 dB
35 -5 -4 -3 -2 -1 0 1 2 POWER AT EACH TONE (dBm) 3 4 5
0 0 200 400 600 800 1000 FREQUENCY (MHz)
Figure 4. Output IP3 vs. Output Power (20, 10, 0, -4 dB gain codes), Tones at 140 MHz and 142 MHz
Figure 7. Noise Figure vs. Frequency (20, 10, 0, -4 dB gain codes)
Rev PrD | Page 6 of 12
Preliminary Technical Data
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 -5 -4
-40C +25C +85C
AD8376
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 -5 -4
-40C +25C +85C
IP3 (dBm)
-3
-2 -1 0 1 2 POWER AT EACH TONE (dBm)
3
4
5
IP3 (dBm)
-3
-2 -1 0 1 2 POWER AT EACH TONE (dBm)
3
4
5
Figure 8. IP3 vs. Power Out over Temperature 20 dB gain code at 110 MHz, 2 MHz spacing
-85
-40C +25C +85C
Figure 11. IP3 vs. Power Out over Temperature 0 dB gain code at 110 MHz, 2 MHz spacing
-85
-40C +25C +85C
-90
-90
HD3 (dBc)
-100
HD3 (dBc) -5 -4 -3 -2 -1 0 1 2 OUTPUT POWER (dBm) 3 4 5
-95
-95
-100
-105
-105
-110
-110 -5 -4 -3 -2 -1 0 1 2 OUTPUT POWER (dBm) 3 4 5
Figure 9. HD3 vs. Power Out over Temperature 20 dB gain code at 110 MHz
-80 -82 -84 -86 HD2 (dBc) HD2 (dBc) -88 -90 -92 -94 -96 -98 -100 -5 -4 -3 -2 -1 0 1 2 OUTPUT POWER (dBm) 3 4 5
-40C +25C +85C
Figure 12. HD3 vs. Power Out over Temperature 0 dB gain code at 110 MHz
-80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -5 -4 -3 -2 -1 0 1 2 OUTPUT POWER (dBm) 3 4 5
-40C +25C +85C
Figure 10.HD2 vs. Power Out over Temperature 20 dB gain code at 110 MHz
Figure 13. HD2 vs. Power Out over Temperature 0 dB gain code at 110 MHz
Rev PrD | Page 7 of 12
AD8376 APPLICATION
HIGH PERFORMANCE ADC DRIVING
The AD8376 provides the gain, isolation, and balanced low distortion output levels for efficiently driving wideband ADCs such as the AD9445. Figure 9 represents a simplified front end of the AD8376 dual VGA driving two AD9445 14 Bit, 125MSPS A/D converters. For optimum performance the AD8376 is driven differentially from the input baluns. The input 37.5 resistors in parallel with the 150 input impedance of the AD8376 provide a 50 differential input impedance. The open collector outputs of the AD8376's are biased through the 1 uH inductors and are ac coupled from the 75 load resistors which are required for gain accuracy. The 75 load resistors are also ac coupled from the AD9445 to negate a DC affect on the input common mode voltage of the AD9445. The series 33 resistors improve the SNR by providing isolation. The AD9445 represents a 1 k differential load and requires a 2 Vp-p differential signal (VREF=1V) between VIN+ and VIN- for a full scale output.
Preliminary Technical Data
This circuit provides variable gain, isolation and source matching for the AD9445. Using this circuit with the AD8376 in a gain of 20 dB (Max Gain) an SFDR performance of 86 dBc is achieved at 100 MHz (see Figure 8).
Figure 14. SFDR Performance of the AD8376 Driving the AD9445
Figure 15. AD8376 Driving the AD9445
Rev PrD | Page 8 of 12
Preliminary Technical Data
EVALUATION BOARD
Figure 10 shows the schematic of the AD8376 evaluation board. The silkscreen and layout of the component and circuit sides are shown in Figure 11 through Figure 14. The board is powered by a single-supply in the 4. 5 V to 5.5 V range. The power supply is decoupled by 10 F and 0.1 F capacitors at each power supply pin. Additional decoupling, in the form of a series resistor or inductor at the supply pins, can also be added. Table 2 details the various configuration options of the evaluation board.
AD8376
The output pins of the AD8376 require supply biasing with 1 H RF chokes. Both the input and output pins must be accoupled. These pins are converted to single-ended with a pair of baluns (Mini-Circuits TC3-1T+ and M/A-COM ETC1-1-13). The baluns at the input, T1 and T2, are used to transform 50 source impedances to the desired 150 reference levels. The output baluns, T3 and T4, and the matching components are configured to provide a 150 to 50 impedance transformations with insertion losses of about 10 dB.
Figure 16. AD8376 Evaluation Board Schematic
Rev PrD | Page 9 of 12
AD8376
Table 2. Evaluation Board Configuration Options
Components C13, C14, C20 to C22, C64 to C67, R90, R91
Preliminary Technical Data
Function Power Supply Decoupling. Nominal supply decoupling consists a 10 F capacitor to ground followed by a 0.1 F capacitor to ground positioned as close to the device as possible. Default Conditions C20 = 10 F (size 3528) C13, C14 = 0.1 F (size 0402) C21, C22, C64 to C67 = 0.1 F (size 0603) R90, R91 = 0 (size 0603) T1, T2 = TC3-1+ (Mini-Circuits) C1 to C4, C60, C61 = 0.1 F (size 0402) R1, R4, R9 to R12 = 0 (size 0402) R2, R3, R70 to R75 = open (size 0402) C7 to C10= 0.1 F (size 0402) L1 to L4 = 1 H (size 0805) T3, T4 = ETC1-1-13 (M/A-COM) R19 to R22 = 61.9 (size 0402) R23, R25, R26, R28 = 30.9 (size 0402) R15 to 18 = 0 (size 0603) R29, R32 = 0 (size 0402) R24, R27, R30, R31, R62, R63 = open (size 0402) C62, C63 = 0.1 F (size 0402) PUA, PUB = installed R13, R14 = 0 (size 0603) C5, C6 = open (size 0603)
T1, T2, C1 to C4, C61, C62, R1 to R4, R9 to R12, R70 to R75
Input Interface. T1 and T2 are 3-to-1 impedance ratio baluns to transform a 50 single-ended input into a 150 balanced differential signal. R1 and R4 ground one side of the differential drive interface for single-ended applications. R9 to R12 and R70 to 75 are provided for generic placement of matching components. C1 to C4 are dc blocks. Output Interface. C7 to C10 are dc blocks. L1 to L4 provide dc biases for the outputs. R19 to R28 are provided for generic placement of matching components. The evaluation board is configured to provide a 150 to 50 impedance transformation with an insertion loss of about 10 dB. T3 and T4 are 1-to-1 impedance ratio baluns to transform the balanced differential signasl to single-ended signals. R29 and R32 ground one side of the differential output interface for single-ended applications.
T3, T4, C7 to C10, L1 to L4, R15 to R32, R62, R63, C62, C63
PUA, PUB, R13, R14, C5, C6
WA0 to WA4, WB0 to WB4
C11, C12
Enable Interface. The AD8376 is enabled by applying a logic high voltage to the ENBA pin for channel A or the ENBB pin for channel B. Channel A is enabled when the PUA switch is set in the "up" position, connecting the ENBA pin to VPOS. Likewise, Channel B is enabled when the PUB switch is set in the "up" position, connecting the ENBB pin to VPOS. Both channels are disabled by setting the switches to the "down" position, connecting ENBA and ENBB pins to GND. Parallel Interface Control. Used to hardwire A0 through A4 and B0 through B4 to the desired gain. The bank of switches, WA0 to WA4, set the binary gain code for channel A. The bank of switches, WB0 to WB4, set the binary gain code for channel B. WA0 and WB0 represent the LSB for each of the respective channels. Voltage Reference. Input Common Mode Voltage ac-coupled to ground by 0.1 F capacitors, C11 and C12.
WA0 to WA4, WB0 to WB4 = installed
C11, C12 = 0.1 F (size 0402)
Rev PrD | Page 10 of 12
Preliminary Technical Data
AD8376
Figure 17. Component Side Silkscreen
Figure 19. Component Side Layout
Figure 18. Circuit Side Silkscreen
Figure 20. Circuit Side Layout
Rev PrD | Page 11 of 12
AD8376 OUTLINE DIMENSIONS
Preliminary Technical Data
Figure2. 32-Lead LFCSP
ORDERING GUIDE
Model AD8376ACPZ-WP AD8376ACPZ-REEL7 AD8376-EVALZ Temperature -40C to +85C -40C to +85C Package Description Waffle Pack, 32 Lead Frame Chip Scale Package 7" Reel, 32 Lead Frame Chip Scale Package Evaluation Board Package Option CP-32-3 CP-32-3
(c) 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06725-0-3/07(PrD)
Rev PrD | Page 12 of 12

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